1. Field of the Invention
The present invention generally relates to bus bridge architectures within processor-based systems, and more particularly to a bus bridge with a programmable early retry capability.
2. Description of the Related Art
A bus provides a mechanism for communication between components of a system or microcontroller. A bus is essentially a collection of wires through which data may be transmitted from one part of a system to another part of the system. In a computer system, for example, a bus connects internal components of the computer to the central processing unit, or CPU, and to main memory.
A system with more than one bus can have a bus bridge to connect a pair of busses together. A bus bridge allows a bus master on one bus to generate transactions to access devices connected to the other bus. For example, a PCI host bridge interface allows a CPU to generate PCI master transactions and allows external PCI bus masters to access memory connected to the CPU. In a conventional bus bridge, a bus master making a read request will control the bus until either the data is supplied to the bus master from the target device or a timeout occurs, at which point the bus master is signaled to retry the transaction and disconnects from the bus, freeing the bus so other transactions can occur. When the bus master next regains the bus, it will retry the read transaction. When the read transaction frequently cannot be completed within the timeout period, a retry capability can improve the latency (the time between a request to access the bus is made and obtaining access to the bus) of bus masters on the bus.
However, if the bus bridge delays signaling the bus master to retry the transaction, the bus remains controlled by the bus master between the time the bus master makes the read request and the time the bus bridge signals a retry cycle, even though other bus masters may have requested access to the bus. If the delay occurs infrequently, holding the bus during the delay period can be better for the bus as a whole than having the bus master give up the bus and retry the transaction. If the delay is frequent or long, however, the bus throughput can be degraded because of the time spent during the delay before the bus master is signaled to retry the transaction. This can occur when a bus master is attempting to access busy resources such as memory.
In a system according to the preferred embodiment, a bus bridge provides a mechanism for causing an external bus master to retry a transaction. The bus bridge is coupled to two busses and provides an automatic retry enable mode. If the automatic retry enable mode is activated, when the external bus master on one bus issues a read request, the bus bridge immediately issues a retry to the external bus master. In one embodiment, when the automatic retry enable mode is activated, the bus bridge treats the read request as a delayed read request and completes the delayed read request asynchronously, supplying data to the external bus master the next time the external bus master retries the read request to the bus bridge following completion of the delayed read request.
One advantage of this mechanism is that the efficiency of the bus is improved by freeing up the bus while the read request is handled by the bus bridge, rather than the bus master holding the bus for up to the maximum number of clocks, and then retrying the transaction when the bus bridge is unable to supply data to complete the read request.